MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 371

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

19.2.1 Master Privilege Register A (AIPSx_MPRA)
The MPRA register specifies identical 4-bit fields defining the access-privilege level
associated with a bus master in the device to the various peripherals. The register
provides one field per bus master.
Freescale Semiconductor, Inc.
4000_004C
4000_005C
4000_006C
4008_002C
4008_004C
4008_005C
4008_006C
4000_0040
4000_0044
4000_0048
4000_0050
4000_0054
4000_0058
4000_0060
4000_0064
4000_0068
4008_0000
4008_0020
4008_0024
4008_0028
4008_0040
4008_0044
4008_0048
4008_0050
4008_0054
4008_0058
4008_0060
4008_0064
4008_0068
Absolute
address
(hex)
Peripheral Access Control Register (AIPS0_PACRE)
Peripheral Access Control Register (AIPS0_PACRF)
Peripheral Access Control Register (AIPS0_PACRG)
Peripheral Access Control Register (AIPS0_PACRH)
Peripheral Access Control Register (AIPS0_PACRI)
Peripheral Access Control Register (AIPS0_PACRJ)
Peripheral Access Control Register (AIPS0_PACRK)
Peripheral Access Control Register (AIPS0_PACRL)
Peripheral Access Control Register (AIPS0_PACRM)
Peripheral Access Control Register (AIPS0_PACRN)
Peripheral Access Control Register (AIPS0_PACRO)
Peripheral Access Control Register (AIPS0_PACRP)
Master Privilege Register A (AIPS1_MPRA)
Peripheral Access Control Register (AIPS1_PACRA)
Peripheral Access Control Register (AIPS1_PACRB)
Peripheral Access Control Register (AIPS1_PACRC)
Peripheral Access Control Register (AIPS1_PACRD)
Peripheral Access Control Register (AIPS1_PACRE)
Peripheral Access Control Register (AIPS1_PACRF)
Peripheral Access Control Register (AIPS1_PACRG)
Peripheral Access Control Register (AIPS1_PACRH)
Peripheral Access Control Register (AIPS1_PACRI)
Peripheral Access Control Register (AIPS1_PACRJ)
Peripheral Access Control Register (AIPS1_PACRK)
Peripheral Access Control Register (AIPS1_PACRL)
Peripheral Access Control Register (AIPS1_PACRM)
Peripheral Access Control Register (AIPS1_PACRN)
Peripheral Access Control Register (AIPS1_PACRO)
Peripheral Access Control Register (AIPS1_PACRP)
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Register name
AIPS memory map (continued)
(in bits)
Width
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Chapter 19 Peripheral Bridge (AIPS-Lite)
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value
4444_4444h
4444_4444h
4444_4444h
4444_4444h
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
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Section/
page
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