MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 395

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

20.5 Initialization/application information
This section provides instructions for initializing the DMA channel MUX.
20.5.1 Reset
The reset state of each individual bit is shown in
summary, after reset, all channels are disabled and must be explicitly enabled before use.
20.5.2 Enabling and configuring sources
Enabling a source with periodic triggering
Configure source #5 transmit for use with DMA channel 2, with periodic triggering
capability
Freescale Semiconductor, Inc.
1. Determine with which DMA channel the source will be associated. Note that only the
2. Clear the CHCFG[ENBL] and CHCFG[TRIG] bits of the DMA channel
3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel
4. Configure the corresponding timer
5. Select the source to be routed to the DMA channel. Write to the corresponding
1. Write 0x00 to CHCFG2 (base address + 0x02)
2. Configure channel 2 in the DMA, including enabling the channel
• Use explicit software re-activation. In this option, the DMA is configured to transfer
• Use a "always enabled" DMA source. In this option, the DMA is configured to
the data using both minor and major loops, but the processor is required to re-activate
the channel (by writing to the DMA registers) after every minor loop. For this option,
the DMA channel should be disabled in the DMA channel MUX.
transfer the data using both minor and major loops, and the DMA channel MUX does
the channel re-activation. For this option, the DMA channel should be enabled and
pointing to an "always enabled" source. Note that the re-activation of the channel can
be continuous (DMA triggering is disabled) or can use the DMA triggering
capability. In this manner, it is possible to execute periodic transfers of packets of
data from one source to another, without processor intervention.
first 4 DMA channels have periodic triggering capability
may be enabled at this point
CHCFG register, ensuring that the CHCFG[ENBL] and CHCFG[TRIG] bits are set
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Chapter 20 Direct memory access multiplexer (DMAMUX)
Memory map/register
definition. In
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