MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 575

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Freescale Semiconductor, Inc.
B1MW[1:0]
Reserved
Reserved
Reserved
Reserved
B1DCE
B1DPE
B1ICE
B1IPE
27–19
18–17
15–8
Field
7–5
16
4
3
2
1
This read-only field defines the number of wait states required to access the bank 1 flash memory.
The relationship between the read access time of the flash array (expressed in system clock cycles) and
RWSC is defined as:
Access time of flash array [system clocks] = RWSC + 1
The FMC automatically calculates this value based on the ratio of the system clock speed to the flash
clock speed. For example, when this ratio is 4:1, the field's value is 3h.
This read-only field is reserved and always has the value zero.
Bank 1 Memory Width
This read-only field defines the width of the bank 1 memory.
00
01
10
11
This read-only field is reserved and always has the value zero.
This read-only field is reserved and always has the value zero.
This read-only field is reserved and always has the value zero.
Bank 1 Data Cache Enable
This bit controls whether data references are loaded into the cache.
0
1
Bank 1 Instruction Cache Enable
This bit controls whether instruction fetches are loaded into the cache.
0
1
Bank 1 Data Prefetch Enable
This bit controls whether prefetches (or speculative accesses) are initiated in response to data references.
0
1
Bank 1 Instruction Prefetch Enable
This bit controls whether prefetches (or speculative accesses) are initiated in response to instruction
fetches.
0
1
Do not cache data references.
Cache data references.
Do not cache instruction fetches.
Cache instruction fetches.
Do not prefetch in response to data references.
Enable prefetches in response to data references.
Do not prefetch in response to instruction fetches.
Enable prefetches in response to instruction fetches.
32 bits
64 bits
Reserved
Reserved
FMC_PFB1CR field descriptions (continued)
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Table continues on the next page...
Description
Chapter 27 Flash Memory Controller (FMC)
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