MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 506

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Restrictions on Watchdog Operation
takes place only when the complete 16-bit value is correctly written, write4. Hence, the
requirement of writing value2 of the sequence within 20 bus clock cycles of value1 is
checked by measuring the gap between write2 and write4.
It is reiterated that the condition for matching values 1 and 2 of the refresh or unlock
sequence remains unchanged. It is just the criterion for detecting a wrong value in these
registers which has been relaxed, as explained, for 8-bit accesses. Any 16-bit access still
needs to adhere to the original guidelines, mentioned in the sections
Watchdog.
23.9 Restrictions on Watchdog Operation
This section mentions some exceptions to the watchdog operation that may not be
apparent to you.
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• Restriction on unlock / refresh operations—In the period between the closure of the
• The update and reload of the watchdog timer happens two to three watchdog clocks
• Clock Switching Delay—The watchdog uses glitch free multiplexers at two places –
• For the windowed mode, there is a two to three bus clock latency between the
• For proper operation of the watchdog, the watchdog clock must be at least five times
• WCT must be equivalent to at least three watchdog clock cycles. If not ensured, this
WCT window (after unlock) and the actual reload of the watchdog timer, unlock and
refresh operations need not be attempted.
after WCT window closes, following a successful configuration on unlock.
one to choose between the LPO oscillator input and alternate clock input and the
other to choose between the watchdog functional clock and fast clock input for
watchdog functional test. A maximum time period of ~ 2 clock A cycles plus ~2
clock B cycles elapses from the time a switch is requested to the occurrence of the
actual clock switch (clock A and B are the two input clocks to the clock mux).
watchdog counter going past the window value and the same registering in the bus
clock domain.
slower than the system bus clock at all times. An exception is the case when the
watchdog clock is synchronous to the bus clock wherein the watchdog clock can be
as fast as the bus clock.
means that even after the close of the WCT window, you have to wait for the
synchronized system reset to deassert in the watchdog clock domain, before
expecting the configuration updates to take effect.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
Refreshing the