MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 528

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Functional Description
1. If entering VLPR mode, MCG has to be configured and enter BLPE mode or BLPI mode with the 4 MHz IRC clock selected
528
Bypassed Low Power
Internal
Bypassed Low Power
External (BLPE)
Stop
Mode
(C2[IRCS]=1). Once in VLPR mode, writes to any of the MCG control registers that can cause a MCG clock mode switch
to a non low power clock mode must be avoided.
(BLPI)1
For the chip-specific modes of operation, refer to the power
management chapter of this MCU.
Bypassed Low Power Internal (BLPI) mode is entered when all the following conditions occur:
In BLPI mode, MCGOUTCLK is derived from the internal reference clock. The FLL is disabled and
PLL is disabled even if the C5[PLLCLKEN] is set to 1.
Bypassed Low Power External (BLPE) mode is entered when all the following conditions occur:
In BLPE mode, MCGOUTCLK is derived from the OSCSEL external reference clock. The FLL is
disabled and PLL is disabled even if the C5[PLLCLKEN] is set to 1.
Entered whenever the MCU enters a Stop state. The power modes are chip specific. For power
mode assignments, see the chapter that describes how modules are configured and MCG behavior
during Stop recovery. Entering Stop mode, the FLL is disabled, and all MCG clock signals are static
except in the following case:
MCGPLLCLK is active in Normal Stop mode when PLLSTEN=1
MCGIRCLK is active in Stop mode when all the following conditions become true:
NOTE:
Description
Table 24-14. MCG Modes of Operation (continued)
• C1[CLKS] bits are written to 01
• C1[IREFS] bit is written to 1
• C6[PLLS] bit is written to 0
• C2[LP] bit is written to 1
• C1[CLKS] bits are written to 10
• C1[IREFS] bit is written to 0
• C2[LP] bit is written to 1
• C1[IRCLKEN] = 1
• C1[IREFSTEN] = 1
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
• When entering Low Power Stop modes (LLS or VLPS) from PEE mode, on exit the
• When entering Normal Stop mode from PEE mode and if C5[PLLSTEN]=0, on exit
MCG clock mode is forced to PBE clock mode, the C1[CLKS] and S[CLKST] will be
configured to 2’b10 and S[LOCK] bit will be cleared without setting S[LOLS].
the MCG clock mode is forced to PBE mode, the C1[CLKS] and S[CLKST] will be
configured to 2’b10 and S[LOCK] bit will clear without setting S[LOLS]. If
C5[PLLSTEN]=1, the S[LOCK] bit will not get cleared and on exit the MCG will
continue to run in PEE mode.
NOTE
Freescale Semiconductor, Inc.