MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 686

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Functional description
31.4 Functional description
The ADC module is disabled during reset, in low power stop mode (refer to the Power
Management information for details), or when the ADCH bits in SC1n are all high. The
module is idle when a conversion has completed and another conversion has not been
initiated. When it is idle and the asynchronous clock output enable is disabled
(ADACKEN is 0), the module is in its lowest power state. The ADC can perform an
analog-to-digital conversion on any of the software selectable channels. All modes
perform conversion by a successive approximation algorithm.
To meet accuracy specifications, the ADC module must be calibrated using the on chip
calibration function. See
When the conversion is completed, the result is placed in the data registers (Rn). The
respective conversion complete flag (COCO) is then set and an interrupt is generated if
the respective conversion complete interrupt has been enabled (AIEN=1).
The ADC module has the capability of automatically comparing the result of a
conversion with the contents of the compare value registers. The compare function is
enabled by setting the ACFE bit and operates with any of the conversion modes and
configurations.
The ADC module has the capability of automatically averaging the result of multiple
conversions. The hardware average function is enabled by setting the AVGE bit and
operates with any of the conversion modes and configurations.
31.4.1 PGA functional description
The Programmable Gain Amplifier (PGA) is designed to increase the dynamic range by
amplifying low-amplitude signals before they are fed to the 16-bit SAR ADC. The gain
of this amplifier is ranged between 1 to 64 in (2^N) steps (1,2,4,8,16,32,64).
This block is designed to work with differential input and output with input signals that
range from 0 -1.2 V ± 10 mV. The output common mode of the PGA is determined based
on the SAR ADC requirement.
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For the chip specific modes of operation, refer to the Power
Management information of this MCU.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Calibration function
NOTE
for details on how to perform calibration.
Freescale Semiconductor, Inc.