MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 461

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

The eDMA design supports the following hardware service request sequence:
The exact timing from this point is a function of the response times for the channel's read
and write accesses. In the case of an internal peripheral bus read and internal SRAM
write, the combined data phase time is 4 cycles. For an SRAM read and internal
peripheral bus write, it is 5 cycles.
Freescale Semiconductor, Inc.
8–11
12
13
14
15
With internal peripheral
bus read and internal
SRAM write
Table 21-294. Hardware service request process, cycles 8–17
Table 21-293. Hardware service request process, cycles 1–7
Cycle
Cycle
5–6
1
2
3
4
7
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
8–12
13
14
15
16
internal peripheral bus
With SRAM read and
write
Table continues on the next page...
eDMA peripheral request is asserted.
The eDMA peripheral request is registered locally in the
eDMA module and qualified. TCDn_CSR[START] bit initiated
requests start at this point with the registering of the user
write to TCDn word 7.
Channel arbitration begins.
Channel arbitration completes. The transfer control descriptor
local memory read is initiated.
The first two parts of the activated channel's TCD is read
from the local memory. The memory width to the eDMA
engine is 64 bits, so the entire descriptor can be accessed in
four cycles.
The first system bus read cycle is initiated, as the third part of
the channel's TCD is read from the local memory. Depending
on the state of the crossbar switch, arbitration at the system
bus may insert an additional cycle of delay here.
The last part of the TCD is read in. This cycle represents the
first data phase for the read, and the address phase for the
destination write.
This cycle represents the data phase of the last destination
write.
The eDMA engine completes the execution of the inner minor
loop and prepares to write back the required TCDn fields into
the local memory. The TCDn word 7 is read and checked for
channel linking or scatter/gather requests.
The appropriate fields in the first part of the TCDn are written
back into the local memory.
The fields in the second part of the TCDn are written back
into the local memory. This cycle coincides with the next
channel arbitration cycle start.
Chapter 21 Direct Memory Access Controller (eDMA)
Description
Description
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