HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 95

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

The DSP unit has DSP status register (DSR). The DSR has conditions of the DSP data operation
result (zero, negative, and so on) and a DC bit which is similar to the T bit in the CPU. The DC bit
indicates the one of the conditional flags. A conditional DSP data processing instruction controls
its execution based on the DC bit. This control affects only the operations in the DSP unit; it
controls the update of DSP registers only. It cannot control operations in CPU, such as address
register updating and load/store operations. The control bit CS[2:0] specifies the condition to be
reflect to the DC bit.
The unconditional DSP type data operations, except PMULS, MOVX, MOVY and MOVS, update
the conditional flags and DC bit, but no CPU instructions, including MAC instructions, update the
DC bit. The conditional DSP type instructions do not update the DSR either.
DSR is assigned as a system register and load/store instructions are prepared as follows:
When DSR is read by the STS instructions, the upper bits (bit 31 to bit 8) are all 0.
STS DSR,Rn;
STS.L DSR,@-Rn;
LDS Rn,DSR;
LDS.L @Rn+,DSR;
MOVS.W,
MOVS.L
Figure 2.8 Connections of DSP Registers and Buses
8 bit
39
7
DSR
A0G
A1G
32
0
MOVX.W
16 bit
16 bit
MOVY.W
31
Rev.6.00 Mar. 27, 2009 Page 37 of 1036
16
M0
M1
A0
A1
X0
X1
Y0
Y1
32 bit
MOVS.W,
MOVS.L
0
REJ09B0254-0600
LDB
XDB
YDB
Section 2 CPU