HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 295

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Bit 1—Module Stop 1 (MSTP1): Specifies halting the clock supply to the realtime clock (RTC)
in the on-chip supporting module. When the MSTP1 bit is set to 1, the clock supply to RTC is
halted. When the clock halts, all RTC registers cannot be accessed, but the counter keeps running.
Bit 1: MSTP1
0
1
Bit 0—Module Stop 0 (MSTP0): Specifies halting the clock supply to the serial communication
interface (SCI) in the on-chip supporting module. When the MSTP0 bit is set to 1, the clock
supply to the SCI is halted.
Bit 0: MSTP0
0
1
9.2.2
The standby control register 2 (STBCR2) is an 8-bit readable/writable register that controls the
operation of the peripheral modules in the normal mode and sleep mode. STBCR is initialized to
H'00 by a power-on reset.
Bit 7— Module Stop 9 (MSTP9): Specifies halting the clock supply to the X/Y memory. When
the MSTP9 bit is set to 1, the clock supply to the X/Y memory is halted. Halting of the clock
supply to the X/Y memory must be controlled by software (any access is not blocked by
hardware).
Bit 7: MSTP9
0
1
Initial value:
Standby Control Register 2 (STBCR2)
R/W:
Bit:
MSTP9 MDCHG MSTP8
Description
RTC runs.
Clock supply to RTC is halted.
Description
SCI runs.
Clock supply to SCI is halted.
Description
X/Y memory runs
Clock supply to X/Y memory is halted
R/W
7
0
R/W
6
0
R/W
5
0
Section 9 Power-Down Modes and Software Reset
MSTP7
R/W
4
0
Rev.6.00 Mar. 27, 2009 Page 237 of 1036
MSTP6
R/W
3
0
MSTP5
R/W
2
0
REJ09B0254-0600
MSTP4
R/W
1
0
(Initial value)
(Initial value)
(Initial value)
—
R
0
0