HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 157

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

3.1.3
Logical Address Space: The SH7727 uses 32-bit logical addresses to access a 4-Gbyte logical
address space that is divided into several areas. Address space mapping is shown in figure 3.2.
In the privileged mode, there are five areas, P0 to P4.
The P0 and P3 areas are mapped onto physical address space in page units, in accordance with
address translation table information. Write-back or write-through can be selected for write access
by means of a CCR setting.
Mapping of the P1 area is fixed in physical address space (H'00000000 to H'1FFFFFFF). In the
P1 area, setting a logical address MSB (bit 31) to 0 generates the corresponding physical address.
P1 area accesses can be cached, and the cache control register (CCR) is set to indicate whether to
cache or not. Write-back or write-through mode can be selected.
Process 1
SH7727 MMU
Physical
memory
Process 1
Process 1
Process 2
Process 3
Figure 3.1 MMU Functions
Physical
memory
Physical
memory
(3)
(1)
Section 3 Memory Management Unit (MMU)
Rev.6.00 Mar. 27, 2009 Page 99 of 1036
Process 1
Process 1
Process 2
Process 3
Virtual
memory
Virtual
memory
MMU
MMU
REJ09B0254-0600
Physical
memory
Physical
memory
(4)
(2)