HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 828

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 25 LCD Controller
Bit 9—CL1 (Horizontal Sync Signal) Control (CL1CNT): Sets whether or not to enable CL1
output during the vertical retrace period.
Bit 9
CL1CNT
0
1
Bit 8—CL2 (Data Latch Clock of LCD Module) Control (CL2CNT): Sets whether or not to
enable CL2 output during the vertical retrace period.
Bit 8
CL2CNT
0
1
Bits 5 to 0—Module Interface Type Select (MIFTYP5 to MIFTYP0): Set the LCD panel type
and data bus width for output to the LCD panel. There are three LCD panel types: STN, DSTN,
and TFT. There are four data bus widths for output to the LCD panel: 4, 8, 12, and 16 bits. When
the required data bus width for a TFT panel is 16 bits or less, connect the LCDC and LCD panel
according to the data bus size of the LCD panel. Unlike in a TFT panel, in an STN or DSTN
panel, the data bus width setting does not have a 1:1 correspondence with the number of display
colors and display resolution, e.g., an 8-bit data bus can be used for 16 bpp, and a 12-bit data bus
can be used for 4 bpp. This is because the number of display colors in an STN or DSTN panel is
determined by how data is placed on the bus, and not by the bus width. For data specifications for
an STN or DSTN panel, see the specifications of the LCD panel used. The output data bus width
should be set according to the mechanical interface specifications of the LCD panel.
If an STN or DSTN panel is selected, display control is performed using a 24-bit space-
modulation FRC (Frame Rate Controller) consisting of the 8-bit R, G, and B included in the
LCDC, regardless of the color and gradation settings. Accordingly, the color and gradation
specified by DSPCOLOR is selected from 16 million colors in an STN or DSTN panel. If a palette
is used, the color specified in the palette is displayed.
Rev.6.00 Mar. 27, 2009 Page 770 of 1036
REJ09B0254-0600
Description
CL1 is output during vertical retrace period
CL1 is inactive during vertical retrace period
Description
CL2 is output during vertical retrace period
CL2 is inactive during vertical and horizontal retrace periods
(Initial value)
(Initial value)