HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 461

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

(1) When channel 0 transfers
(2) When channel 1 transfers
(3) When channel 2 transfers
(4) When channel 3 transfers
Initial priority order
Initial priority order
Initial priority order
Priority order
afrer transfer
Priority order
afrer transfer
Priority order
afrer transfer
Priority order
afrer transfer
Priority order
afrer transfer
Post-transfer priority order
when there is an
immediate transfer
request to channel 1 only
Figure 14.3 Operation in Round-Robin Mode
CH0 > CH1 > CH2 > CH3
CH0 > CH1 > CH2 > CH3
CH0 > CH1 > CH2 > CH3
CH0 > CH1 > CH2 > CH3
CH0 > CH1 > CH2 > CH3
CH3 > CH0 > CH1 > CH2
CH2 > CH3 > CH0 > CH1
CH1 > CH2 > CH3 > CH0
CH2 > CH3 > CH0 > CH1
Section 14 Direct Memory Access Controller (DMAC)
Rev.6.00 Mar. 27, 2009 Page 403 of 1036
Channel 2 becomes bottom
priority.
The priority of channels 0 and 1,
which were higher than channel 2,
are also shifted. If immediately
after there is a request to transfer
channel 1 only, channel 1 becomes
bottom priority and the priority of
channels 0 and 3, which were
higher than channel 1, are also
shifted.
Channel 0 becomes bottom
priority
Channel 0 becomes bottom
priority.
The priority of channel 0, which
was higher than channel 3, is also
shifted.
Initial priority order
REJ09B0254-0600