HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 181

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

3.5.6
When MMU exception or CPU address error occurs immediately before or within a repeat loop,
the PC of the instruction that generated the exception can not be saved in SPC correctly and repeat
loop can not be restarted after returning from exception handler. EXPEVT is set to H'070 in cases
of TLB miss, TLB invalid, and CPU address error. EXPEVT is set to H'0D0 in case of TLB
protection violation. Figure 3.14 describes the places where this case occurs.
In a repeat loop of 4 or more instructions, only the last 4 instructions are relevant (see figure 3.14
(4)).
MMU Exception in Repeat Loop
(2) 2 instructions repeated (inst1 and inst2, SR.RC=2)
(1) 1 instruction repeated (inst1, SR.RC=2)
(3) 3 instructions repeated (inst1, inst2 and inst3, SR.RC=2)
inst-1
inst0
inst1
inst2
inst1
inst2
inst3
inst-1
inst0
inst1
inst1
inst2
inst-1
inst0
inst1
inst2
inst3
inst1
inst2
inst3
inst4
Figure 3.14 MMU Exception in Repeat Loop
IF
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: Exception source stage where SPC is not correct
and repeat loop can not be restarted
EX MA WB
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Section 3 Memory Management Unit (MMU)
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Rev.6.00 Mar. 27, 2009 Page 123 of 1036
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REJ09B0254-0600