HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 488

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 14 Direct Memory Access Controller (DMAC)
Conditions for Individual-Channel Ending: When one of the following conditions is satisfied,
transfer in the corresponding channel ends.
When the value in the DMA transfer count register (DMATCR) is 0
When the DE bit in CHCR is cleared to 0.
• When DMATCR is 0: When the DMATCR value reaches 0, the DMA transfer in the
• When DE in CHCR is 0: When the DE bit in CHCR is cleared, the DMA transfer in the
Conditions for All-Channel Ending: When one of the following conditions is satisfied, transfer
in all channels end simultaneously.
When the NMIF (NMI flag) bit in DMAOR is set to 1
When the DME bit in DMAOR is cleared to 0.
• When the NMIF bit in DMAOR is set to 1: When an NMI interrupt occurs, the NMIF bit in
• When DME is cleared to 0 in DMAOR: Clearing the DME bit to 0 in the DMAOR forcibly
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REJ09B0254-0600
corresponding channel ends and the transfer end flag bit (TE) in CHCR is set. If the IE
(interrupt enable) bit is set at this time, a DMAC interrupt (DEI) is requested to the CPU. The
conditions described in (a) to (d) above are not applied for this transfer ending.
corresponding channel stops. The conditions described in (a) to (d) above are not applied for
this transfer ending.
DMAOR is set to 1 and all channels stop their transfers according to the conditions in (a) to (d)
described above, and pass the bus right to another bus master. Consequently, even if the NMI
bit is set to 1 during transfer, the SAR, DAR, DMATCR are updated. Then the TE bit is not
set. To resume the transfer after the NMI interrupt exception handling, clear the NMIF bit to 0.
At this time, for the channels that should not be restarted, clear the corresponding DE bit in
CHCR.
aborts the transfers on all channels. Then the TE bit is not set. All channels abort their transfers
according to the conditions (a) to (d) described in section 14.3.7, DMAC Transfer Ending, in
the same way as that at the generation of an address error by the DMAC or NMI interrupt
generation. In this case, the values in SAR, DAR, and DMATCR are also updated.