HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 651

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

•
Figure 19.5 shows a sample serial transmission flowchart. After SCIF transmission is enabled, use
the following procedure to perform serial data transmission.
Serial data transmission
read 1 from TDFE bit and TEND flag
trigger set number) to SCFTDR2,
Write transmit data (16 - transmit
Clear TE bit in SCSCR2 to 0
Read TEND bit in SCSSR2
Set SCPDR2 and SCPCR2
Read TDFE bit in SCSSR2
in SCSSR2, then clear to 0
All data transmitted?
End of transmission
Start transmission
Break output?
TEND= 1?
TDFE= 1?
Figure 19.5 Sample Serial Transmission Flowchart
Yes
Yes
Yes
Yes
(3)
Section 19 Serial Communication Interface with FIFO (SCIF)
No
No
No
No
(1)
(2)
(1) SCIF status check and transmit data write:
(2) Serial transmission continuation procedure:
(3) Break output at the end of serial
Read serial status register 2 (SCSSR2) and
check that the TDFE flag is set to 1, then
write transmit data to the transmit FIFO
data register 2 (SCFTDR2), read 1 from the
TDFE and TEND flags, then clear these
flags to 0.
The number of transmit data bytes that can
be written is 16 - (transmit trigger set
number).
To continue serial transmission, read 1 from
the TDFE flag to confirm that writing is
possible, then write data to SCFTDR2, and
then clear the TDFE flag to 0.
transmission:
To output a break in serial transmission, set
the port SC data register (SCPDR) and port
SC control register (SCPCR), then clear the
TE bit to 0 in the serial control register 2
(SCSCR2). For information on SCPDR2
and SCPCR2, see section 17.2.8.
In steps 1 and 2, it is possible to ascertain
the number of data bytes that can be
written from the number of transmit data
bytes in SCFTDR indicated by the upper 8
bits of the FIFO data count set register 2
(SCFDR2).
Rev.6.00 Mar. 27, 2009 Page 593 of 1036
REJ09B0254-0600