HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 55

SH3-DSP, LEAD FREE

HD6417727F100CV

Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417727F100CV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
Table 18.3
Table 18.4
Table 18.5
Table 18.6
Table 18.7
Table 18.8
Table 18.9
Section 19 Serial Communication Interface with FIFO (SCIF)
Table 19.1
Table 19.2
Table 19.3
Table 19.4
Table 19.5
Table 19.6
Table 19.7
Table 19.8
Table 19.9
Section 20 Serial IO (SIOF)
Table 20.1
Table 20.2
Table 20.3
Table 20.4
Table 20.5
Table 20.6
Table 20.7
Table 20.8
Table 20.9
Table 20.10 Receive Request Submit Condition........................................................................ 640
Table 20.11 Transmit or Receive Reset ..................................................................................... 645
Table 20.12 SIOF Interrupt Factors............................................................................................ 646
Table 20.13 Setting Conditions for the Transmit or Receive Interrupt Flag .............................. 647
Section 21 Analog Front End Interface (AFEIF)
Table 21.1
Table 21.2
Table 21.3
Register Settings for the Smart Card Interface ....................................................... 551
Relationship of n to CKS1 and CKS0 .................................................................... 553
Examples of Bit Rate B (Bit/s) for SCBRR Settings (n = 0).................................. 553
Examples of SCBRR Settings for Bit Rate B (Bit/s) (n = 0).................................. 553
Maximum Bit Rates for Frequencies (Smart Card Interface Mode)....................... 554
Register Set Values and SCK0 Pin......................................................................... 554
Smart Card Mode Operating State and Interrupt Sources ...................................... 561
SCIF Pins ............................................................................................................... 568
Registers................................................................................................................. 569
SCSMR2 Settings................................................................................................... 581
Bit Rates and SCBRR2 Settings............................................................................. 581
Maximum Bit Rates for Various Frequencies with Baud Rate Generator
(Asynchronous Mode)............................................................................................ 585
SCSMR2 Settings and SCIF Transmit/Receive ..................................................... 589
Settings for SCSMR2 and SCSCR2 and Selection of Clock Source of SCIF ........ 590
Serial Transmit/Receive Formats ........................................................................... 590
SCIF Interrupt Sources........................................................................................... 600
SIOF Pin List.......................................................................................................... 607
SIOF Register Configuration.................................................................................. 607
Examples of SIOF Clock Frequency...................................................................... 630
Serial Transmit Mode............................................................................................. 632
Frame Length ......................................................................................................... 633
Transmit Data Sound Mode ................................................................................... 635
Receive Data Sound Mode ..................................................................................... 635
Control Data Channel Number Establishment ....................................................... 636
Transmit Request Submit Condition ...................................................................... 639
Pins for AFE Interface............................................................................................ 659
AFEIF Registers..................................................................................................... 659
Telephone Number and Data.................................................................................. 669
Rev.6.00 Mar. 27, 2009 Page liii of lvi
REJ09B0254-0600

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