HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 627

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

19.1.4
Table 19.2 summarizes the SCIF internal registers. These registers specify the data format and bit
rate, and control the transmitter and receiver sections.
Table 19.2 Registers
Register Name
Serial mode register 2
Bit rate register 2
Serial control register 2
Transmit FIFO data register 2
Serial status register 2
Receive FIFO data register 2
FIFO control register 2
FIFO data count set register 2
Notes: These registers are located in area 1 of physical space. Therefore, when the cache is on,
either access these registers from the P2 area of logical space or else make an appropriate
setting using the MMU so that these registers are not cached.
1. Only 0 can be written to clear the flag.
2. When address translation by the MMU does not apply, the address in parentheses
Register Configuration
should be used.
SCBRR2
SCSCR2
SCFTDR2
SCFCR2
SCFDR2
Abbreviation
SCSMR2
SCSSR2
SCFRDR2
Section 19 Serial Communication Interface with FIFO (SCIF)
R/W
R/W
R/W
W
R
R/W
R
R/W
R/(W) *
Rev.6.00 Mar. 27, 2009 Page 569 of 1036
1
Initial
Value
H'00
H'FF
H'00
—
H'0060
Undefined H'0400015A
H'00
H'0000
H'04000150
H'04000152
H'04000154
H'04000156
Address
(H'A4000150) *
(H'A4000152) *
(H'A4000154) *
(H'A4000156) *
H'04000158
(H'A4000158) *
(H'A400015A) *
H'0400015C
(H'A400015C) *
H'0400015E
(H'A400015E) *
REJ09B0254-0600
2
2
2
2
2
2
2
2
Access
Size
8 bits
8 bits
8 bits
8 bits
16 bits
8 bits
8 bits
16 bits