HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 705

SH3-DSP, LEAD FREE

HD6417727F100CV

Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417727F100CV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
It depends on setting of SIIER register whether or not an interrupt corresponding to each interrupt
factor is submitted or not depend. SIOF submits each interrupt when interrupt factor that 1 is set to
corresponding bit of SIIER register is set to 1.
(2) Transmit/Receive Interrupt Flag
Transmit or receive interrupt requests INTC or DMAC to accept the interruption through the
interrupt flag, which is generated from the value of TDREQ bit and RDREQ bit in SISTR register.
Table 20.13 shows the setting conditions for the transmit or receive interrupt flag.
Table 20.13 Setting Conditions for the Transmit or Receive Interrupt Flag
Transmit interrupt flag
Receive interrupt flag
(3) Operations in Case of Error
SIOF executes the following operations for the errors which are shown in SISTR as status.
• Transmit FIFO under run (TFUDR): The data that was transmitted directly before is sent
• Transmit FIFO over run (TFOVR): The contents of transmit FIFO is protected, the written data
• Receive FIFO over run (RFOVR): Data that became to over flow is disposed and vanished.
• Receive FIFO under run (RFUDR): Data that is read as final data is output on bus. (indefinite
• FS error (FSERR): Internal counter is reset according to the sync. signal that became to error.
again.
that became to over flow is ignored.
in specification)
Setting Conditions
TDREQ in SISTR register = 1
RDREQ in SISTR register = 1
Rev.6.00 Mar. 27, 2009 Page 647 of 1036
Resetting Conditions
TDREQ in SISTR register = 0
Acknowledge from DMAC
RDREQ in SISTR register = 0
Acknowledge from DMAC
Section 20 Serial IO (SIOF)
REJ09B0254-0600

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