HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 1036

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 32 Electrical Characteristics
32.3.9
Table 32.12 H-UDI-Related Pin Timing
Conditions: VccQ = 2.6 to 3.6 V, Vcc = 1.60 to 2.05 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C
Item
TCK cycle time
TCK high pulse width
TCK low pulse width
TCK rise/fall time
TRST setup time
TRST hold time
TDI setup time
TDI hold time
TMS setup time
TMS hold time
TDO delay time
ASEMD0 setup time
ASEMD0 hold time
Rev.6.00 Mar. 27, 2009 Page 978 of 1036
REJ09B0254-0600
H-UDI-Related Pin Timing
TCK (input)
1/2 V
Figure 32.47 TCK Input Timing
cc
Q
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
TCKcyc
TCKH
TCKL
TCKf
TRSTS
TRSTH
TDIS
TDIH
TMSS
TMSH
TDOD
ASEMDH
ASEMDS
V
IH
t
TCKH
V
t
IH
TCKcyc
Min
50
12
12
—
12
50
10
10
10
10
—
12
12
t
TCKf
V
t
IL
TCKL
V
IL
Max
—
—
—
4
—
—
—
—
—
—
19
—
—
1/2 V
t
V
TCKf
IH
Unit
ns
ns
ns
ns
ns
t
ns
ns
ns
ns
ns
ns
ns
cyc
cc
Q
Figure
Figure 32.47
Figure 32.48
Figure 32.49
Figure 32.50