HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 672

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 20 Serial IO (SIOF)
Bits 11 to 8—Receive Data for Left Channel Slot Assignment (RDLA3 to RDLA0): The slot
assignment of received data for left channel in received frame is specified from 0000(0: initial
value) to 1110(14) by this register. The receive data for left channel is stored in bits 15 to 0 in
SIRDL of SIRDR register.
Note: The operation of this LSI is unpredictable when setting 1111 in bits RDLA3 to RDLA0.
Bit 7—Receive Data for Right Channel Enable (RDRE)
Bit 7: RDRE
0
1
Bits 3 to 0—Receive Data for Right Channel Slot Assignment (RDRA3 to RDRA0): The slot
assignment of received data for right channel in received frame is specified from 0000(0: initial
value) to 1110(14) by this register. The receive data for right channel is stored in bits 15 to 0 in
SIRDR of SIRDR register.
Note: The operation of this LSI is unpredictable when setting 1111 in bits RDRA3 to RDRA0.
20.2.5
This register specifies the position of control command in each frame. The setting to this register
is enabled when 1*** is set to bits FL3 to FL0 of SIMDR register. This register is initialized at
power on reset or software reset.
Bits 14 to 12, and 6 to 4—Reserved
Rev.6.00 Mar. 27, 2009 Page 614 of 1036
REJ09B0254-0600
Initial value:
Initial value:
R/W:
R/W:
Control Command Assign Register (SICDAR)
Bit:
Bit:
CD0E
CD1E
R/W
R/W
15
0
7
0
Description
Disable receiving of right channel data
Enable receiving of right channel data
14
—
—
R
R
0
6
0
13
—
—
R
R
0
5
0
12
—
—
R
R
0
4
0
CD0A3
CD1A3
R/W
R/W
11
0
3
0
CD1A2
R/W2
R/W
R/W
10
0
2
0
CD1A1
R/W1
R/W
R/W
9
0
1
0
(Initial value)
CD1A0
R/W0
R/W
R/W
8
0
0
0