HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 658
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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Section 19 Serial Communication Interface with FIFO (SCIF)
19.4
The SCIF has four interrupt sources: transmit-FIFO-data-empty (TXI), receive-error (ERI),
receive-data-full (RXI), and break (BRI).
Table 19.9 shows the interrupt sources and their order of priority. The interrupt sources are
enabled or disabled by means of the TIE and RIE bits in SCSCR2. A separate interrupt request is
sent to the interrupt controller for each of these interrupt sources.
When the TDFE flag in the serial status register 2 (SCSSR2) is set to 1, a TXI interrupt request is
generated. The DMAC can be activated and data transfer performed when this interrupt is
generated. The TDFE flag is cleared when data exceeding the transmit trigger number is written
to transmit FIFO data register 2 (SCFTDR2) by the DMAC, 1 is read from TDFE, and then 0 is
written to TDFE.
When the RDF flag in SCSSR2 is set to 1, an RXI interrupt request is generated. The DMAC can
be activated and data transfer performed when the RDF flag in SCSSR is set to 1. The RDF flag is
cleared when receive data is read from receive FIFO data register 2 (SCFRDR2) by the DMAC
until the quantity of receive data in SCFRDR2 is less than the receive trigger number, 1 is read
from RDF, and then 0 is written to RDF.
When the ER flag in SCSSR2 is set to 1, an ERI interrupt request is generated.
When the BRK flag in SCSSR2 is set to 1, a BRI interrupt request is generated.
The TXI interrupt indicates that transmit data can be written, and the RXI interrupt indicates that
there is receive data in SCFRDR2.
Table 19.9 SCIF Interrupt Sources
Interrupt
Source
ERI
RXI
BRI
TXI
See section 4, Exception Processing, for priorities and the relationship with non-SCIF interrupts.
Rev.6.00 Mar. 27, 2009 Page 600 of 1036
REJ09B0254-0600
SCIF Interrupts
Description
Interrupt initiated by receive error flag (ER)
Interrupt initiated by receive data FIFO full flag
(RDF) or data ready flag (DR)
Interrupt initiated by break flag (BRK)
Interrupt initiated by transmit FIFO data empty flag
(TDFE)
Impossible
DMAC
Activation
Possible
(RDF only)
Impossible
Possible
Priority on
Reset Release
High
Low
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