HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 931

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

28.4.4
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time t
shows the A/D conversion timing. Table 28.4 indicates the A/D conversion time.
As indicated in figure 28.6, the A/D conversion time includes t
length of t
time therefore varies within the ranges indicated in table 28.4.
In multi mode and scan mode, the values given in table 28.4 apply to the first conversion. In the
second and subsequent conversions the conversion time is fixed at 536 states when CKS = 0 or
266 states when CKS = 1.
In all cases, the CKS bit in ADCSR should be set according to the frequency of P
conversion time is within the range shown in table 32.16 in section 32, Electrical Characteristics.
(1)
(2)
t
t
t
D
SPL
CONV
Input sampling timing
: ADCSR write cycle
: ADCSR address
: A/D conversion start delay
: Input sampling time
: A/D conversion time
Input Sampling and A/D Conversion Time
D
varies depending on the timing of the write access to ADCSR. The total conversion
D
Write signal
after the ADST bit of ADCSR is set to 1, then starts conversion. Figure 28.6
Address
ADF
Pφ
(1)
Figure 28.6 A/D Conversion Timing
(2)
t
D
t
SPL
t
CONV
Rev.6.00 Mar. 27, 2009 Page 873 of 1036
D
and the input sampling time. The
Section 28 A/D Converter
REJ09B0254-0600
φ
so that the