HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 730

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 21 Analog Front End Interface (AFEIF)
(2) Ringing Interrupt Timing
As the figure 21.3 shows, the ringing signal from the line is transformed to rectangular wave and
then input to AFEIF. The interrupt is generated at the rising edge of input wave in AFEIF module.
(3) Dial Pulse Interrupt Timing
Dial pulse interrupt is generated in the dial pulse transmit sequence when AFEIF reads 0H (end)
data from DPNQ register or all of 4 digits are output. Refer to section 21.3.3, DAA Interface about
dial pulse sequence.
Rev.6.00 Mar. 27, 2009 Page 672 of 1036
REJ09B0254-0600
Ringing wave
Input wave
AFE_FS
AFE_FS
AFE_TX
OUT
TFE/TTE
AFE_RX
IN
RFF/RTF
Figure 21.3 Ringing Interrupt Occurrence Timing
Data 1
INT. occur
First
Figure 21.2 FIFO Interrupt Timing
Data 2
First+1
Half−1
Half−1
Half
Half