HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 356

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 12 Bus State Controller (BSC)
12.2.3
Wait state control register 1 (WCR1) is a 16-bit read/write register that specifies the number of
idle (wait) state cycles inserted for each area. For some memories, the drive of the data bus may
not be turned off quickly even when the read signal from the external device is turned off. This
can result in conflicts between data buses when consecutive memory accesses are to different
memories or when a write immediately follows a memory read. This LSI automatically inserts idle
states equal to the number set in WCR1 in those cases.
WCR1 is initialized to H'3FF3 by a power-on reset. It is not initialized by a manual reset or by
standby mode.
Bit 15—WAIT Sampling Timing Select (WAITSEL): Specifies the WAIT signal sampling
timing.
Bit 15: WAITSEL
0
1
Note: * If low level is input to the WAIT by setting the WAITSEL bit, the LSI operation cannot be
Bits 14, 3, and 2 —Reserved: These bits are always read as 0. The write value should always be
0.
Rev.6.00 Mar. 27, 2009 Page 298 of 1036
REJ09B0254-0600
Initial value:
R/W: R/W
Bit:
guaranteed.
Wait State Control Register 1 (WCR1)
WAIT
SEL
15
0
14
—
R
0
Description
Set to 1 when WAIT signal is used.*
Sampled at the falling edge of CKIO.
R/W
IW1
A6
13
1
R/W
IW0
A6
12
1
R/W
IW1
11
A5
1
R/W
IW0
A5
10
1
R/W
IW1
A4
9
1
R/W
IW0
A4
1
8
R/W
IW1
A3
7
1
R/W
IW0
A3
1
6
R/W
IW1
A2
5
1
R/W
IW0
A2
1
4
—
R
3
0
(Initial value)
—
R
2
0
R/W
IW1
A0
1
1
R/W
IW0
A0
0
1