HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 507

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

15.2.4
The TMU has a total of three timer counters (TCNT), one for each channel. The TCNT counters
are 32-bit read/write registers that are decremented according to the input clock. The input clock
can be selected with the TPSC2 to TPSC0 bits in the timer control register (TCR).
When a TCNT decrementation results in an underflow (H'00000000 → H'FFFFFFFF), the
underflow flag (UNF) in the timer control register (TCR) of the relevant channel is set. The TCOR
value is simultaneously set in TCNT itself and the decrementation continues from that value.
The TCNT counter is a 32-bit readable/writable register. Because the internal bus for the SH7727
on-chip peripheral modules is 16 bits wide, a time lag occurs when reading data from 32-bit
registers because the upper 16 bits and lower 16 bits are read separately. Since TCNT counts
sequentially, this time lag can create discrepancies between the data in the upper and lower halves.
To prevent this, a buffer register is connected to TCNT so that upper and lower halves are not read
separately. Thus all 32 bits in TCNT can thus be read at once and no timing discrepancies occur
when reading data.
Initial value:
Initial value:
Initial value:
Initial value:
Timer Counters (TCNT)
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
R/W
R/W
R/W
R/W
31
23
15
1
1
1
7
1
R/W
R/W
R/W
R/W
30
22
14
1
1
1
6
1
R/W
R/W
R/W
R/W
29
21
13
1
1
1
5
1
R/W
R/W
R/W
R/W
28
20
12
1
1
1
4
1
Rev.6.00 Mar. 27, 2009 Page 449 of 1036
R/W
R/W
R/W
R/W
27
19
11
1
1
1
3
1
R/W
R/W
R/W
R/W
26
18
10
Section 15 Timer (TMU)
1
1
1
2
1
REJ09B0254-0600
R/W
R/W
R/W
R/W
25
17
1
1
9
1
1
1
R/W
R/W
R/W
R/W
24
16
1
1
8
1
0
1