HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 689

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

20.3.2
(1) SIOFSYNC
SIOFSYNC is the frame sync signal, and supports the two modes shown below.
• The pulse with 1 bit width which shows the first of the sync pulse frame.
• The pulse with 1/2 frame width, which shows left channel in L/R stereo data as high and right
Figure 20.3 shows synchronized timing as SIOFSYNC. Figure 20.3(a) shows the case for master
mode 1, slave mode 1, and slave mode 2. Figure 20.3(b) shows the case for master mode 2.
channel as low.
(a) At the synch pulse
(b) At the L/R
SCK_SIO
SIOFSYNC
TXD_SIO
RXD_SIO
SCK_SIO
SIOFSYNC
TXD_SIO
RXD_SIO
Serial Timing
1 bit delay
No delay
Figure 20.3 SIOF Serial Data Synchronized Timing
Lch. first bit data (MSB)
First bit data (MSB)
1/2 frame length
1 frame
1 frame
Rev.6.00 Mar. 27, 2009 Page 631 of 1036
Rch. first bit data (MSB)
1/2 frame length
Section 20 Serial IO (SIOF)
REJ09B0254-0600