HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 392

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 12 Bus State Controller (BSC)
Table 12.12 Relationship between Synchronous DRAM type, bus width and AMX
32 bits 256 Mbits 4M × 16-bit × 4-bank*
16 bits 512 Mbits 8M × 16-bit × 4-bank*
Notes: * L/H is a bit used to specify commands. It is fixed to L or H by the access mode.
Rev.6.00 Mar. 27, 2009 Page 334 of 1036
REJ09B0254-0600
Width
Bus
128 Mbits 1M × 32-bit × 4-bank*
64 Mbits
256 Mbits 4M × 16-bit × 4-bank
128 Mbits 2M × 16-bit × 4-bank
64 Mbits
: Bank address
Memory Type
2M × 16-bit × 4-bank*
4M × 8-bit × 4-bank*
1M × 16-bit × 4-bank*
2M × 8-bit × 4-bank*
4M × 4-bit × 4-bank*
512K × 32-bit × 4-bank
8M × 8-bit × 4-bank*
1M × 16-bit × 4-bank
2M × 8-bit × 4-bank
1
0
0
0
0
0
0
0
1
1
1
0
0
0
Setting
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
1
1
1
0
1
0
0
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
Output Timing
Column address
Row address
Column address
Row address
Column address
Row address
Column address
Row address
Column address
Row address
Column address
Row address
Column address
Row address
Column address
Row address
Column address
Row address
Column address
Row address
Column address
Row address
Column address
Row address
Column address
Row address
Column address
Row address
A1–A8
A10–A17
A1–A8
A9–A16
A1–A8
A10–A17
A1–A8
A11–A18
A1–A8
A9–A16
A1–A8
A10–A17
A1–A8
A11–A18
A1–A8
A9–A16
A1–A8
A11–A18
A1–A8
A10–A17
A1–A8
A11–A18
A1–A8
A10–A17
A1–A8
A9–A16
A1–A8
A10–A17
A1 to A8
A9
A9
A18 A19 A20 A21 A22 A23 A24 A25
A9
A17 A18 A19 A20 A21 A22 A23 A16
A9
A18 A19 A20 A21 A22 A23 A24 A16
A9
A19 A20 A21 A22 A23 A24 A25 A16
A9
A17 A18 A19 A20 A21 A22 A23 A16
A9
A18 A19 A20 A21 A22 A23 A24 A16
A9
A19 A20 A21 A22 A23 A24 A25 A16
A9
A17 A18 A19 A20 A21 A22 A23 A16
A9
A19 A20 A21 A22 A23 A24 A25 A16
A9
A18 A19 A20 A21 A22 A23 A24 A16
A9
A19 A20 A21 A22 A23 A24 A25 A16
A9
A18 A19 A20 A21 A22 A23 A24 A16
A9
A17 A18 A19 A20 A21 A22 A23 A16
A9
A18 A19 A20 A21 A22 A23 A24 A16
External Address Pin
A10 A11 A12 A13 A14 A15 A16
A10 A11 L/H
A10 A11 L/H
A10 A11 L/H
A10 A11 L/H
A10 A11 L/H
A10 A11 L/H
A10 A11 L/H
A10 A11 L/H
A10 L/H
A10 L/H
A10 L/H
A10 L/H
A10 L/H
A10 L/H
A12 A13 A24 A25 A16
A12 A22 A23 A24 A16
A12 A23 A24 A25 A16
A12 A22 A23 A24 A16
A12 A21 A22 A15 A16
A12 A22 A23 A15 A16
A13 A23 A24 A25
A13 A22 A23 A16
A13 A23 A24 A16
A13 A24 A25 A16
A13 A22 A23 A16
A13 A23 A24 A16
A13 A24 A25 A16
A21 A22 A15 A16