HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 464

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 14 Direct Memory Access Controller (DMAC)
(1) Direct address transfer mode
Rev.6.00 Mar. 27, 2009 Page 406 of 1036
REJ09B0254-0600
DMA transfer requires two bus cycles because data is read from the transfer source in a data
read cycle and written to the transfer destination in a data write cycle. At this time, transfer
data is temporarily stored in the DMAC. In the transfer between external memories as shown
in figure 14.5, data is read from one external memory to the DMAC in a data read cycle, and
then that data is written to the other external memory in a write cycle. Figures 14.6 to 14.8
show examples of this operation timing
Data is read from the transfer source module using the SAR value as
the address, and the read data is stored in the DMAC temporarily.
The value stored in the DMAC is written to the transfer destination
module using the DAR value as the address.
Data buffer
Data buffer
DMAC
DMAC
SAR
DAR
SAR
DAR
Figure 14.5 Operation in Direct Address Mode
Second bus cycle
First bus cycle
Transfer destination
Transfer destination
Transfer source
Transfer source
Memory
Memory
module
module
module
module