HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 501
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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15.1
This LSI has an on-chip 32-bit timer unit (TMU) comprised of three 32-bit timer channels
(channels 0 to 2).
15.1.1
The TMU has the following features:
• Auto-reload 32-bit down-counters for each channel
• Auto-reload 32-bit constant registers and 32-bit down counters that can be read or written to at
• Interrupt request generation at the counter underflow:
• Selection of six counter input clocks for each channel:
• All channels can operate when the SH7727 is in standby mode:
• Synchronized read:
• The maximum 2 MHz operating frequency for the 32-bit counter in each channel:
any time for each channel
Interrupt requests can be generated when the 32-bit down counter underflows (H'00000000 →
H'FFFFFFFF) in each channel.
On-chip RTC output clock (16 kHz), Pφ/4, Pφ/16, Pφ/64, and Pφ/256
When the RTC output clock is used as the counter input clock, the count operation is normally
performed in standby mode.
TCNT is a 32-bit register that is successively modified. Since the internal bus for the SH7727
on-chip supporting modules is 16 bits wide, a time lag can occur between the time when the
upper 16 bits and lower 16 bits are read. To correct the discrepancy in the counter read value
caused by this time lag, a synchronization circuit is built in the TCNT so that the entire 32-bit
data in the TCNT can be read at once.
Operate the SH7727 so that the clock input to each channel timer counter does not exceed the
maximum operating frequency, by dividing the external clock and peripheral clock (Pφ) with
the prescaler.
Overview
Features
Section 15 Timer (TMU)
Rev.6.00 Mar. 27, 2009 Page 443 of 1036
Section 15 Timer (TMU)
REJ09B0254-0600
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