HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 671

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Bit 6—Transmit Left Channel Data Repeatedly (TLREP): Setting of this bit is effective when
TDRE bit is 1. When 1 is set to this bit, setting of bits 15 to 0 in SITDR register is ignored.
Bit 6: TLREP
0
1
Bits 3 to 0—Transmit Data for Right Channel Slot Assignment (TDRA3 to TDRA0): The slot
assignment of transmit data for Right channel in transmit frame is specified from 0000(0: initial
value) to 1110(14) by this register. The transmit data for right channel is set in SITDR bits 15 to 0
in SITDR register.
Note: The operation of this LSI is unpredictable when setting 1111 in bits TDRA3 to TDRA0.
20.2.4
This register specifies the data assignment of received data in each received frame. This register is
initialized at power on reset or software reset.
Bits 14 to 12, and 6 to 4—Reserved
Bit 15—Receive Data for Left Channel Enable (RDLE)
Bit 15: RDLE
0
1
Initial value:
Initial value:
R/W:
R/W:
Receive Data Assign Register (SIRDAR)
Bit:
Bit:
RDRE
RDLE
R/W
R/W
15
0
7
0
Description
The data in SITDR bit of SITDR register is transmitted as right channel data.
The data in SITDL bit of SITDL register is transmitted as right channel data.
Description
Disable receiving of left channel data
Enable receiving of left channel data
14
—
—
R
R
0
6
0
13
—
—
R
R
0
5
0
12
—
—
R
R
0
4
0
Rev.6.00 Mar. 27, 2009 Page 613 of 1036
RDRA3
RDLA3
R/W
R/W
11
0
3
0
RDRA2
RDLA2
Section 20 Serial IO (SIOF)
R/W
R/W
10
0
2
0
RDRA1
RDLA1
REJ09B0254-0600
R/W
R/W
9
0
1
0
(Initial value)
(Initial value)
RDRA0
RDLA0
R/W
R/W
8
0
0
0