HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 512

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 15 Timer (TMU)
15.4.2
The status flag is cleared when 0 is written by the CPU. Figure 15.7 shows the timing.
15.4.3
The TMU generates underflow interrupts for each channel. When the interrupt request flag and
interrupt enable bit are both set to 1, the corresponding interrupt is requested. When an interrupt is
generated, codes are set in the interrupt event register (INTEVT, INTEVT2). Provide the
appropriate interrupt handling according to the codes.
The channel priority can be changed using the interrupt controller (see section 4, Exception
Handling, and section 7, Interrupt Controller (INTC)). Table 15.2 lists TMU interrupt sources.
Table 15.2 TMU Interrupt Sources
Channel
0
1
2
Rev.6.00 Mar. 27, 2009 Page 454 of 1036
REJ09B0254-0600
Peripheral address bus
Status Flag Clear Timing
Interrupt Sources and Priorities
Interrupt Source
TUNI0
TUNI1
TUNI2
UNF
Pφ
Figure 15.7 Status Flag Clear Timing
Description
Underflow interrupt 0
Underflow interrupt 1
Underflow interrupt 2
T1
TCR write cycle
TCR address
T2
T3
Priority
High
Low