HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 629

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

19.2.3
The transmit shift register 2 (SCTSR2) transmits serial data. The SCI loads transmit data from the
transmit FIFO data register 2 (SCFTDR2) into the SCTSR2, then transmits the data serially from
the TxD2 pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the
next transmit data from the SCFTDR2 into the SCTSR2 and starts transmitting again. The CPU
cannot read or write the SCTSR2 directly.
19.2.4
The transmit FIFO data register 2 (SCFTDR2) is a 16-byte 8-bit-length FIFO register that stores
data for serial transmission. When the SCIF detects that the transmit shift register (SCTSR2) is
empty, it moves transmit data written in the SCFTDR2 into the SCTSR2 and starts serial
transmission. Continuous serial transmission is performed until the transmit data in the SCFTDR2
becomes empty. The CPU can always write to the SCFTDR2.
When the transmit data in the SCFTDR2 is full (16 bytes), next data cannot be written. If
attempted to write, the data is ignored.
Transmit Shift Register 2 (SCTSR2)
Transmit FIFO Data Register 2 (SCFTDR2)
R/W:
R/W:
Bit:
Bit:
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W
7
7
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W
6
6
Section 19 Serial Communication Interface with FIFO (SCIF)
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Rev.6.00 Mar. 27, 2009 Page 571 of 1036
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