HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 594

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 17 Serial Communication Interface (SCI)
Transfer direction
Synchronization
clock
Serial
Bit 7
Bit 0
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
data
RDRF
ORER
ERI interrupt
RXI interrupt
RXI interrupt
Reads data with
request generated
request
request
the RXI interrupt
by overrun error
generated
generated
processing routine
and clears RDRF
bit to 0
1 frame
Figure 17.22 Example of SCI Operation in Reception
Transmitting and Receiving Serial Data Simultaneously (Clock Synchronous Mode)
Figure 17.23 shows a sample flowchart for simultaneous serial transmit and receive operations.
After enabling the SCI transmission/reception, provide simultaneous serial transmit and receive
operations following the procedure shown below:
Rev.6.00 Mar. 27, 2009 Page 536 of 1036
REJ09B0254-0600