HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 708

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 20 Serial IO (SIOF)
(5) A Case of 16 bits Stereo (No.2)
L/R method, rising edge sampling and Lch.transmit data are assigned to slot No. 0, Lch. receive
data are assigned to slot No.1, Lch. receive data are assigned to slot No. 2, Rch. receive data is
assigned to slot No. 3, and frame length is 64 bits.
(6) A Case of 16 bits Stereo (No. 3)
Sync pulse method, falling edge sampling and Lch. data are assigned to slot No. 0, Rch. data is
assigned to slot No. 2, control ch. data 0 is assigned to slot No. 1, control ch. data 0 is assigned to
slot No. 3, and frame length is 128 bits.
Rev.6.00 Mar. 27, 2009 Page 650 of 1036
REJ09B0254-0600
SCK_SIO
SIOFSYNC
TXD_SIO
RXD_SIO
SCK_SIO
SIOFSYNC
TXD_SIO
RXD_SIO
Setting: TRMD = 00 or 10, REDG = 0,
Setting: TRMD = 11, REDG = 1,
TDLE = 1,
RDLE = 1,
CD0E = 1,
Figure 20.17 Transmit or Receive Timing (16 bits stereo—2)
Figure 20.18 Transmit or Receive Timing (16 bits stereo—3)
TDLE = 1,
RDLE = 1,
CD0E = 0,
Lch. DATA Control ch. 0 Rch. DATA Control ch. 1
Slot No.0 Slot No.1 Slot No.2 Slot No.3 Slot No.4 Slot No.5 Slot No.6 Slot No.7
Lch. DATA
1 bit delay
Slot No.0
No delay
TDLA3 to TDLA0 = 0000,
RDLA3 to RDLA0 = 0001,
CD0A3 to CD0A0 = 0000,
TDLA3 to TDLA0 = 0000,
RDLA3 to RDLA0 = 0000,
CD0A3 to CD0A0 = 0001,
Lch. DATA
Slot No.1
1 frame
1 frame
Rch. DATA
Slot No.2
FL = 1101 (frame length 64 bits),
TDRE = 1,
RDRE = 1,
CD1E = 0,
FL = 1110 (frame length 128 bits),
TDRE = 1,
RDRE = 1,
CD1E = 1,
TDRA3 to TDRA0 = 0010,
RDRA3 to RDRA0 = 0011,
CD1A3 to CD1A0 = 0000
Rch. DATA
Slot No.3
TDRA3 to TDRA0 = 0010,
RDRA3 to RDRA0 = 0010,
CD1A3 to CD1A0 = 0011