HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 760

SH3-DSP, LEAD FREE

HD6417727F100CV

Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417727F100CV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
Section 23 USB Function Controller
23.5.17 USB Interrupt Select Register 0 (USBISR0)
USBISR0 selects the interrupt event register (INTEVT2) codes of the interrupt requests indicated
in USB interrupt flag register 0. If the USB issues an interrupt request to the INTC when the
corresponding bit in USBISR0 is cleared to 0, the interrupt will be USBFI0 (USB function
interrupt 0), with an interrupt event register (INTEVT2) code of H'A20. If the USB issues an
interrupt request to the INTC when the corresponding bit in USBISR0 is set to 1, the interrupt will
be USBFI1 (USB function interrupt 1), with an interrupt event register (INTEVT2) code of
H'A40. The initial value designates an interrupt event register (INTEVT2) code of H'A20. If
interrupts occur simultaneously, USBFI0 has priority by default. For details on the interrupt event
register (INTEVT2), refer to section 4, Exception Handling, and section 7, Interrupt Controller
(INTC).
23.5.18 USB Interrupt Select Register 1 (USBISR1)
USBISR1 selects the interrupt event register (INTEVT2) codes of the interrupt requests indicated
in USB interrupt flag register 1. If the USB issues an interrupt request to the INTC when the
corresponding bit in USBISR1 is cleared to 0, the interrupt will be USBFI0 (USB function
interrupt 0), with an interrupt event register (INTEVT2) code of H'A20. If the USB issues an
interrupt request to the INTC when the corresponding bit in USBISR1 is set to 1, the interrupt will
be USBFI1 (USB function interrupt 1), with an interrupt event register (INTEVT2) code of
H'A40. The initial value designates an interrupt event register (INTEVT2) code of H'A20. If
interrupts occur simultaneously, USBFI0 has priority by default. For details on the interrupt event
register (INTEVT2), refer to section 4, Exception Handling, and section 7, Interrupt Controller
(INTC).
Rev.6.00 Mar. 27, 2009 Page 702 of 1036
REJ09B0254-0600
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
BSRT
R/W
R
7
0
7
0
FULL
R/W
EP1
R
6
0
6
0
EP2
R/W
TR
R
5
0
5
0
EMPTY
EP2
R/W
R
4
0
4
0
SETUP
R/W
TS
R
3
0
3
0
EP0o
R/W
R/W
EP3
TS
TR
2
0
2
1
EP0i
R/W
EP3
R/W
TR
TS
1
0
1
1
VBUS
EP0i
R/W
R/W
TS
0
0
0
1

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