HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 824

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 25 LCD Controller
Register Name
LCDC fetch data line address offset
register for display panel
LCDC palette control register
LCDC palette data registers 00 to FF
LCDC horizontal character number
register
LCDC horizontal synchronization signal
register
LCDC vertical displayed line number
register
LCDC vertical total line number register
LCDC vertical synchronization signal
register
LCDC ac modulation signal toggle line
number register
LCDC interrupt control register
LCDC power management mode
register
LCDC power supply sequence period
register
LCDC control register
Note: * When the LCDC is not a target for address conversion by the MMU, use the addresses in parentheses.
Rev.6.00 Mar. 27, 2009 Page 766 of 1036
REJ09B0254-0600
LDLAOR
LDPALCR
LDPR00–FF
LDHCNR
LDHSYNR
LDVDLNR
LDVTLNR
LDVSYNR
LDACLNR
LDINTR
LDPMMR
LDPSPR
LDCNTR
Abbreviation
Initial Value
H’0280
H’0000
Undefined
H’4F52
H’0050
H’01DF
H’01DF
H’01DF
H’000C
H’0000
H’0010
H’F60F
H’0000
Address
H’04000C10
(H’A4000C10)*
H’04000C12
(H’A4000C12)*
H’04000800 to
H’04000BFC
(H’A4000800 to
H’A4000BFC)*
H’04000C14
(H’A4000C14)*
H’04000C16
(H’A000C16)*
H’04000C18
(H’A4000C18)*
H’04000C1A
(H’A4000C1A)*
H’04000C1C
(H’A4000C1C)*
H’04000C1E
(H’A4000C1E)*
H’04000C20
(H’A4000C20)*
H’04000C24
(H’A4000C24)*
H’04000C26
(H’A4000C26)*
H’04000C28
(H’A4000C28)*
Access Size
16
16
32
16
16
16
16
16
16
16
16
16
16