HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 388

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 12 Bus State Controller (BSC)
Sampling is performed at the transition from the Tw state to the T2 state; therefore, if the WAIT
signal has no effect if asserted in the T1 cycle or the first Tw cycle.
The WAIT signal is sampled at the falling edge of the clock. If the setup time and hold times with
respect to the falling edge of the clock are not satisfied, the value sampled at the next falling edge
is used..
However, the WAIT signal is ignored in the following three cases:
• When writing to an external address area using DMA 16-byte transfer in dual address mode
• When transferring data from a DACK-equipped external device to an external address area
• During cache write-back access
Rev.6.00 Mar. 27, 2009 Page 330 of 1036
REJ09B0254-0600
Figure 12.10 Basic Interface Wait State Timing (Wait State Insertion by WAIT Signal
using DMA 16-byte transfer in dual address mode
Write
Read
A25 to A0
RD/WR
WAIT
RD
D31 to D0
WEn
D31 to D0
CKIO
BS
CSn
T1
WAITSEL = 1)
Tw
Tw
Wait states inserted
by WAIT signal
Tw
T2