HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 486

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 14 Direct Memory Access Controller (DMAC)
The reload function can be used for the 8-, 16- and 32-bit data transfer.
DMATCR2, which specifies a transfer count, is incremented by 1 each time a transfer ends
regardless of the reload function setting. Consequently, be sure to specify the value multiple of
four in DMATCR2 when the reload function is on. If other values are specified, correct operation
is not guaranteed.
The counters that count transfers of four times for the reload function are reset by clearing the
DME bit in DMAOR or the DE bit in CHCR2, by setting the transfer end flag (TE bit in CHCR2),
by inputting an NMI, besides by a reset or in standby mode. However, the SAR2, DAR2,
DMATCR2 registers are not reset. Therefore, the above reset source is generated, some counters
are initialized but some are not in the DMAC, which may cause a malfunction when the DMAC is
restarted. To avoid this problem, if a reset source except the TE bit setting is generated when the
reload function is used, set SAR2, DAR2, and DMATCR2 again.
Rev.6.00 Mar. 27, 2009 Page 428 of 1036
REJ09B0254-0600
address bus
data bus
Internal
Internal
CK
Figure 14.25 Timing Chart of Source Address Reload Function
First transfer of
SAR2
SAR2 output
DAR2 output
channel 2
DAR2
SAR2 data
SAR2+2
Second transfer
SAR2+2 output
DAR2 output
DAR2
SAR2+2 data
SAR2+4
SAR2+4 output
Third transfer
DAR2 output
DAR2
SAR2+4 data
SAR2+6
SAR2+6 output
Fourth transfer
DAR2 output
SAR2 reload
SAR2 output
DAR2 output
DAR2
SAR2+6 data
Fifth transfer
SAR2