HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 1004

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 32 Electrical Characteristics
32.3.2
Table 32.9 Control Signal Timing
Conditions: VccQ = 2.6 to 3.6 V, Vcc = 1.60 to 2.05 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C
Notes: 1. RESETP, NMI and IRQ5 to IRQ0 are asynchronous. Changes are detected at the
Rev.6.00 Mar. 27, 2009 Page 946 of 1036
REJ09B0254-0600
RESETP pulse width
RESETP setup time *
RESETP hold time
RESETM pulse width
RESETM setup time
RESETM hold time
BREQ setup time
BREQ hold time
NMI setup time *
NMI hold time
IRQ5–IRQ0 setup time *
IRQ5–IRQ0 hold time
BACK delay time
STATUS1, STATUS0 delay time
Bus tri-state delay time 1
Bus tri-state delay time 2
Bus buffer-on time 1
Bus buffer-on time 2
2. In the standby mode, t
3. In the standby mode, t
Control Signal Timing
clock fall when the setup shown is used. When the setup cannot be used, detection
can be delayed until the next clock falls. When using as IRL, please observe the setup
time.
When the clock multiplication ratio is changed, t
low until STATUS (0-1) changes to reset (HH). When the clock multiplication ratio is
changed, RESETM must be kept low until STATUS (0-1) changes to reset (HH).
1
1
1
RESPW
RESMW
= t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
= t
RESPW
RESPS
RESPH
RESMW
RESMS
RESMH
BREQS
BREQH
NMIS
NMIH
IRQS
IRQH
BACKD
STD
BOFF1
BOFF2
BON1
BON2
OSC2
OSC2
(10 ms). In the sleep mode, t
(10 ms). In the sleep mode, RESETM must be kept
Min
20 *
23
2
12 *
3
34
10
3
10
4
10
4
—
—
0
0
0
0
2
3
RESPW
Max
—
—
—
—
—
—
—
—
—
—
—
—
10
16
15
15
15
15
= t
PLL1
(100 µs).
tcyc
ns
ns
tcyc
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RESPW
= t
Figure
32.13
32.14
32.15
32.14
32.15
32.16
PLL1
(100 µs).