HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 788

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 24 USB HOST Module
Register: HcControl
Bits
7, 6
5
4
Rev.6.00 Mar. 27, 2009 Page 730 of 1036
REJ09B0254-0600
Reset
00b
0b
0b
R/W
R/W
R/W
R/W
Offset: 04–07
Description
HostControllerFunctionalState (HCFS)
HCD determines whether the host controller has started to route
SOF after having read the StartofFrame bit of
HcInterruptStatus. This bit can be changed by the host
controller only in the UsbSuspend state. The host controller can
move from the UsbSuspend state to the UsbResume state after
having detected the resume signal from the downstream port. In
the host controller, UsbSuspend is entered after the software
reset so that UsbReset is entered after the hardware reset. The
former resets the route hub.
00: USB reset
01: USB resume
10: USB operation
11: USB suspend
BulkListEnable (BLE)
This bit is set to enable the processing of the bulk list in the next
frame. The host controller checks this bit when the processing
of the list has been determined. When disabling, HCD can
correct the list. When HcBulkCurrentED indicates ED to be
deleted, HCD should hasten the pointer by updating
HcBulkCurrentED before re-enabling the list processing.
0: Bulk list processing is not carried out. (initial value)
1: Bulk list processing is carried out.
ControlListEnable (CLE)
This bit is set to enable the processing of the control list in the
next frame. If cleared by HCD, the processing of the control list
is not carried out after next SLF. The host controller must check
this bit whenever the list will be processed. When disabling,
HCD can correct the list. When HcControlCurrentED indicates
ED to be deleted, HCD should hasten the pointer by updating
HcBulk before re-enabling the list processing.
0: Control list processing is not carried out. (initial value)
1: Control list processing is carried out.