HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 682

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 20 Serial IO (SIOF)
20.2.9
This register allows SIOF interrupt resources to issue interrupt to CPU. When 1 is written to each
bit, corresponding interrupt is issued by SIOF. This register is initialized at power on reset, or
software reset.
Note: * 0 should be written into these bits. Otherwise the operation is unpredictable.
Bits 15, 11, and 7 to 5—Reserved
Bit 14—Transmit Control Data Ready Enable (TCRDYE)
Bit 14: TCRDYE
0
1
Bit 13—Transmit FIFO Empty Enable (TFEMPE)
Bit 13: TFEMPE
0
1
Bit 12—Transmit Data Transfer Request Enable (TDREQE)
Bit 12: TDREQE
0
1
Rev.6.00 Mar. 27, 2009 Page 624 of 1036
REJ09B0254-0600
Initial value:
Initial value:
R/W:
R/W:
Interrupt Enable Register (SIIER)
Bit:
Bit:
R*
R*
15
—
—
0
7
0
Description
Disable interrupt of transmit control data ready
Enable interrupt of transmit control data ready (control interrupt)
Description
Disable interrupt of transmit FIFO empty
Enable interrupt of transmit FIFO empty (control interrupt)
Description
Disable interrupt of transmit data transfer request enable
Enable interrupt of transmit data transfer request enable (transmit interrupt)
TCRDYE TFEMPE TDREQE
R/W
R*
14
—
0
6
0
R/W
R*
13
—
0
5
0
FSERRE TFOVRE TFUDRE RFUDRE RFOVRE
R/W
R/W
12
0
4
0
R/W
R*
11
—
0
3
0
RCRDYE RFFULE RDREQE
R/W
R/W
10
0
2
0
R/W
R/W
9
0
1
0
(Initial value)
(Initial value)
(Initial value)
R/W
R/W
8
0
0
0