HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 345

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Pin Name
Data enable 3
Read
Wait
Clock enable
IOIS16
Bus release request
Bus release
acknowledgment
Mode selection
12.1.4
The BSC has 11 registers (table 12.2). The synchronous DRAM also has a built-in synchronous
DRAM mode register. These registers control direct connection interfaces to memory, wait states,
and refreshes.
Register Configuration
Signal
WE3/DQMUU/
ICIOWR
RD
WAIT
CKE
IOIS16
BREQ
BACK
MD5 to MD3
I/O
Output
Output
Input
Output
Input
Input
Output
Input
Description
When memory other than synchronous
DRAM and PCMCIA is used, selects D31
to D24 write strobe signal. When
synchronous DRAM is used, selects D31 to
D24. When PCMCIA is used, strobe signal
indicating I/O write.
Strobe signal indicating read cycle
Wait state request signal
Clock enable control signal of synchronous
DRAM
Signal indicating PCMCIA 16-bit I/O. Valid
only in little-endian mode.
Bus release request signal
Bus release acknowledge signal
Specifies bus width and endian of area 0
Rev.6.00 Mar. 27, 2009 Page 287 of 1036
Section 12 Bus State Controller (BSC)
REJ09B0254-0600