HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 823

SH3-DSP, LEAD FREE

HD6417727F100CV

Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417727F100CV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
25.1.3
Table 25.1 summarizes the LCDC’s pin configuration.
Table 25.1 Pin Configuration
Name
LCD 15−0
DON
CL1
CL2
M/DISP
FLM
VCPWC
VEPWC
LCLK
Note: Check the LCD module specifications carefully in section 25.4, Clock and LCD Data Signal
25.1.4
Table 25.2 summarizes the configuration of the LCDC’s registers.
Table 25.2 Register Configuration
Register Name
LCDC input clock register
LCDC module type register
LCDC data format register
LCDC scan mode register
LCDC data fetch start address register
for upper portion of display panel
LCDC data fetch start address register
for lower portion of display panel
Examples, before deciding on the wiring specifications for the LCD module.
Pin Configuration
Register Configuration
I/O
O
O
O
O
O
O
O
O
I
Function
Data for LCD panel
Display-on signal (DON)
Shift-clock 1 (STN/DSTN)/Horizontal sync signal (HSYNC) (TFT)
Shift-clock 2 (STN/DSTN)/dot clock (DOTCLOCK) (TFT)
LCD current-alternation signal/(STN/DSTN),
Display enable BLANK (TFT)/DISP signal
First line marker/Vertical sync signal (VSYNC) (TFT)
LCD-module power control (Vcc)
LCD-module power control (V
LCD clock-source input
Abbreviation
LDICKR
LDMTR
LDDFR
LDSMR
LDSARU
LDSARL
Initial Value
H’0101
H’0109
H’000C
H’0000
H’0C000000
H’0C000000
Rev.6.00 Mar. 27, 2009 Page 765 of 1036
EE
)
H’04000C00
(H’A4000C00)*
H’04000C02
(H’A4000C02)*
H’04000C04
(H’A4000C04)*
H’04000C06
(H’A4000C06)*
H’04000C08
(H’A4000C08)*
H’04000C0C
(H’A4000C0C)*
Address
Section 25 LCD Controller
REJ09B0254-0600
Access Size
16
16
16
16
32
32

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