HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 645

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Bit 3—Modem Control Enable (MCE): Enables the modem control signals CTS2 and RTS2.
Bit 3: MCE
0
1
Note: * The CTS2 is fixed to active 0 regardless of the input value, and the RTS2 is also fixed to 0.
Bit 2—Transmit FIFO Data Register Reset (TFRST): Disables the transmit data in the transmit
FIFO data register 2 and resets the data to the empty state.
Bit 2: TFRST
0
1
Note: * Reset is operated in resets or the standby mode.
Bit 1—Receive FIFO Data Register Reset (RFRST): Disables the receive data in the receive
FIFO data register 2 and resets the data to the empty state.
Bit 1: RFRST
0
1
Note: * Reset is operated in resets or the standby mode.
Bit 0—Loop Back Test (LOOP): Internally connects the transmit output pin (TXD2) and receive
input pin (RXD2) and enables the loop back test.
Bit 0: LOOP
0
1
Description
Disables the modem signal*
Enables the modem signal
Description
Disables reset operation*
Enables reset operation
Description
Disables reset operation*
Enables reset operation
Description
Disables the loop back test
Enables the loop back test
Section 19 Serial Communication Interface with FIFO (SCIF)
Rev.6.00 Mar. 27, 2009 Page 587 of 1036
REJ09B0254-0600
(Initial value)
(Initial value)
(Initial value)
(Initial value)