HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 200
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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Section 4 Exception Handling
• TLB invalid exception
• TLB exception/CPU address error in repeat loop
• Initial page write exception
Rev.6.00 Mar. 27, 2009 Page 142 of 1036
REJ09B0254-0600
To speed up TLB miss processing, the offset differs from other exceptions.
⎯ Conditions: Comparison of TLB addresses shows address match but V = 0.
⎯ Operations: The logical address (32 bits) that caused the exception is set in TEA and the
The PC and SR of the instruction that generated the exception are saved in the SPC and SSR,
respectively. If the exception occurred during a read, H'040 is set in EXPEVT; if the exception
occurred during a write, H'060 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1
and a branch occurs to PC = VBR + H'0100.
⎯ Conditions: TLB miss, TLB invalid or CPU address error in the last several instructions of
⎯ Operations: TEA, PTEH and RC bit in MMUCR are set in the way of the type of
The SR of the instruction that generated the exception are saved in the SSR. But the SPC is not
the PC of the instruction that generated the exception. Repeat loop can not be restarted after
returning from exception handler. In order to complete a repeat loop, ensure not to cause TLB
exceptions or CPU address error in the last several instructions of repeat loop (see section
3.5.6, MMU Exception in Repeat Loop). If the TLB exception or CPU address error occurred
in the last several instructions of repeat loop, H'070 is set in EXPEVT. The BL, MD, and RB
bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100.
⎯ Conditions: A hit occurred to the TLB for a store access, but D = 0.
⎯ Operations: The logical address (32 bits) that caused the exception is set in TEA and the
The PC and SR of the instruction that generated the exception are saved to the SPC and SSR,
respectively. H'080 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a
branch occurs in PC = VBR + H'0100.
corresponding virtual page number (22 bits) is set in PTEH (31 to 10). The ASID of PTEH
indicates the ASID at the time the exception occurred. The way that generated the
exception is set in the RC bits in MMUCR.
repeat loop (see section 3.5.6, MMU Exception in Repeat Loop)
exception.
This occurs for initial writes to the page registered by the load.
corresponding virtual page number (22 bits) is set in PTEH (31 to 10). The ASID of PTEH
indicates the ASID at the time the exception occurred. The way that generated the
exception is set in the RC bit in MMUCR.
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