HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 492

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 14 Direct Memory Access Controller (DMAC)
Bits 1 and 0—Clock Select 1, 0 (CKS1, CKS0): These bits select the clock input to CMCNT
from four clocks which are divided from the peripheral clock (Pφ). When the STR0 bit in CMSTR
is set to 1, the CMCNT0 starts incrementation with the clock selected by CKS1 and CKS0.
Bit 1: CKS1
0
Compare-Match Counter 0 (CMCNT0)
The compare-match counter 0 (CMCNT0) is a 16-bit register that is used as an up-counter.
When the clock is selected with the CKS1 and CKS0 bits in CMCSR0 and the STR0 bit in
CMSTR is set to 1, CMCNT0 starts incrementation with the selected clock. When the CMCNT0
value matches that in the compare-match constant register 0 (CMCOR0), the CMCNT0 is cleared
to H'0000 and the CMF flag in CMCSR0 is set to 1.
CMCNT0 is initialized to H'0000 by a reset, but it retains its previous values in standby mode.
Rev.6.00 Mar. 27, 2009 Page 434 of 1036
REJ09B0254-0600
1
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Bit 0: CKS0
0
1
0
1
R/W
R/W
15
0
7
0
R/W
R/W
14
0
6
0
Description
Pφ/4
Pφ/8
Pφ/16
Pφ/64
R/W
R/W
13
0
5
0
R/W
R/W
12
0
4
0
R/W
R/W
11
0
3
0
R/W
R/W
10
0
2
0
R/W
R/W
0
0
9
1
(Initial value)
R/W
R/W
8
0
0
0