HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 554

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 17 Serial Communication Interface (SCI)
Bit 6—Receive Data Register Full (RDRF): Indicates that SCRDR contains received data.
Bit 6: RDRF
0
1
Note: The SCRDR and RDRF are not affected by detection of receive errors or by clearing of the
Bit 5—Overrun Error (ORER): Indicates that data reception aborted due to an overrun error.
Bit 5: ORER
0
1
Notes: 1. Clearing the RE bit to 0 in the serial control register does not affect the ORER bit, which
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REJ09B0254-0600
RE bit to 0 in the serial control register. They retain their previous contents.
If RDRF is still set to 1 when reception of the next data ends, an overrun error (ORER)
occurs and the received data is lost.
2. SCRDR continues to hold the data received before the overrun error, so subsequent
retains its previous value.
receive data is lost. Serial receiving cannot continue while ORER is set to 1. In the
clock synchronous mode, serial transmitting is also disabled.
Description
SCRDR does not contain valid received data
[Clear conditions]
1. When the chip is reset or enters standby mode
2. When software reads RDRF after it has been set to 1, then writes 0 in RDRF.
SCRDR contains valid received data
[Setting condition]
When serial data is received normally and transferred from SCRSR to SCRDR.
Description
Receiving is in progress or has ended normally *
[Clear conditions]
1. When the chip is reset or enters standby mode
2. When ORER=1 is read and then 0 is written to ORER.
A receive overrun error occurred *
[Setting condition]
When reception of the next serial data ends when RDRF is set to 1.
2
1
(Initial value)
(Initial value)