HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 801

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

24.2.14 HcFmInterval
HcFmInterval Register (H'04000434)
The HcFmInterval register includes a 14-bit value indicating the bit time interval of the frame (i.e.,
between two serial SOFs) and a 15-bit value indicating the maximum packet size at a full speed
that is transmitted and received by the host controller without causing scheduling overrun. The
host controller driver adjusts the frame interval minutely by writing a new value over the current
value in each SOF. This supplies required programming ability to the host controller to
synchronize with an external clock source and to synchronize with offset of an unknown local
clock.
Register: HcFmInterval
Bits
31
30–16
15–14
13–0
Reset
0b
0h
0h
2EDFh
R/W
R/W
R/W
—
R/W
Offset: 34–37
Description
FrameIntervalToggle (FIT)
This bit is toggled by HCD whenever it loads a new value into
FrameInterval.
FSLargestDataPacket (FSMPS)
This field specifies a value which is loaded into the Largest Data
Packet Counter at the beginning of each frame.
The counter value expresses the largest data amount of the bit
that can be transmitted and received in one transaction by the
host controller at any given time without causing scheduling
overrun. The field value is calculated by HCD.
Reserved.
FrameInterval (FI)
These bits specifies the interval between two serial SOFs with
bit times. The nominal value is set to 11999. HCD must store
the current value of this field before resetting the host controller.
With this procedure, this bit is reset to its nominal value by the
host controller by setting the HostControllerReset bit in the
HcCommandStatus register. HCD can select to restore the
stored value at the completion of the reset sequence.
Rev.6.00 Mar. 27, 2009 Page 743 of 1036
Section 24 USB HOST Module
REJ09B0254-0600