HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 718

SH3-DSP, LEAD FREE

HD6417727F100CV

Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417727F100CV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
Section 21 Analog Front End Interface (AFEIF)
21.2
21.2.1
ACTR is the control register for AFEIF and is composed of ACTR1 and ACTR2. ACTR1 is
mainly used for FIFO control commands. ACTR2 is used for AFE control commands and DAA
control commands.
(1) AFEIF Control Register 1 (ACTR1)
Bits 14 to 8, 6, and 5—Reserved
Bit 15—AFE Hardware Control Bit (HC): This bit controls AFE. AFE_HC1 signal is made to
high directly often the next serial transmit data transfer, when this bit is written to 1. Then ACDR
data (AFE control word) is transferred by founding the second AFE.FS. AFEIF module
automatically makes AFE_HC1 signal to low and HC bit to 0, directly after transferring the AFE
control word. See section 21.3.2, AFE Interface for more detail about AFE control sequences.
Bit 7—FIFO Digital Loop Back (DLB)
Bit 7: DLB
0
1
Rev.6.00 Mar. 27, 2009 Page 660 of 1036
REJ09B0254-0600
Initial value:
Initial value:
R/W:
R/W:
Register Description
AFEIF Control Register 1 and 2 (ACTR1, ACTR2)
Bit:
Bit:
R/W
DLB
R/W
HC
15
0
7
0
Description
Normal operation
Digital loop back between Tx FIFO and Rx FIFO is performed. In this time the
transmit data is output to AFE_TXOUT, too.
14
R
R
0
6
0
13
R
R
0
5
0
FFSZ2
R/W
12
R
0
4
0
FFSZ1
R/W
11
R
0
3
0
FFSZ0
R/W
10
R
0
2
0
R/W
TE
R
9
0
1
0
(Initial value)
R/W
RE
R
8
0
0
0

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