HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 637

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Bit 1—Receive FIFO Data Full (RDF): Indicates that received data is transferred to the receive
FIFO data register 2 (SCFRDR2), the quantity of data in SCFRDR2 becomes more than the
number of receive triggers specified by the RTRG1 and RTRG0 bits in FIFO control register 2
(SCFCR2).
Bit 1: RDF
0
1
Note: * Since SCFTDR2 is a 16-byte FIFO register, the maximum quantity of data which can be
Bit 0—Receive Data Ready (DR): Indicates that the receive FIFO data register 2 (SCFRDR2)
stores the data which is less than the specified number of receive triggers, and that next data is not
yet received after 15 ETU has elapsed from the last stop bit.
Bit 0: DR
0
1
Note: * This is equivalent to 1.5 frames with the 8-bit 1-stop-bit format. (ETU: Element Time Unit)
read when RDF is 1 is the specified number of receive triggers. If attempted to read after
all data in the SCFRDR2 have been read, the data is undefined. The quantity of receive
data in SCFRDR2 is indicated by the lower 8 bits of SCFTDR2.
Description
The quantity of transmit data written to SCFRDR2 is less than the specified
number of receive triggers.
RDF is cleared to 0 at power-on reset or in standby mode, or when SCFRDR2 is
read until the quantity of receive data in SCFRDR2 is less than the specified
receive trigger number, and software reads 1 from RDF and then writes 0 to
RDF.
The quantity of receive data in SCFRDR2 is more than the specified number of
receive triggers.
RDF is set to 1 when the quantity of receive data which is greater than the
specified number of receive triggers is stored in SCFRDR2.*
Description
Receive is in progress, or no received data remains in SCFRDR2 after
completing receive normally.
DR is cleared to 0 when the chip is power-on reset or enters standby mode, or
software reads DR after it has been set to 1, then writes 0 in DR.
Next receive data is not received.
DR is set to 1 when SCFRDR2 stores the data which is less than the specified
number of receive triggers, and that next data is not yet received after 15 ETU
has elapsed from the last stop bit.*
Section 19 Serial Communication Interface with FIFO (SCIF)
Rev.6.00 Mar. 27, 2009 Page 579 of 1036
REJ09B0254-0600
(Initial value)
(Initial value)